The present invention relates to the field of testing of memory for a digital computer. In particular, this invention relates to a pseudo-random memory test.
There are a number of known schemes for testing computer memories. One prior art method is to write all binary ones or zeros into a memory and then to read from the memory, checking for errors. One problem with that prior art method is its inability to detect whether two or more data lines are shorted together.
Another prior art method is to remain at each memory address long enough to write and read a series of data words at that address, wherein each data word comprises zeros and a single one, and the data words differ in the position of that single one bit. The one bit "walks" through each bit position as the data words are written into and read from the memory. One shortcoming of that prior art method is that it cannot detect whether or not two or more address lines are shorted together, and other prior art testing systems that write the same data into different addresses share the inability to detect whether or not two or more address lines are shorted together.
Some prior art memory testers use a simple increment by one counter to generate memory addresses. Some prior art memory testers employ more than one address counter. One problem with some prior art testers using counters is that some address bits generated by the counter or counters remain the same for relatively long periods of time before changing state.
One prior art method of memory testing known as the Galpat test involves staying at one address while changing data patterns that are written into and read from that address, and then moving onto and doing the same at other addresses. The amount of time it takes to run a Galpat test on a memory is generally proportional to the square of the number of memory addresses tested. Therefore, the amount of time it takes to run a Galpat test increases dramatically for larger memories with significantly more memory addresses.
One prior art way to check data for errors is to use comparators to check the data read from the memory against the data that was written into the memory. The addition of many comparators for testing to an existing circuit design can, however, take up otherwise valuable space on a printdd circuit board or within an integrated circuit.
Another prior art way to check data for errors is to check parity. Various prior art error detecting and correcting codes can be employed, including the Hamming code. The Hamming code offers the ability to detect errors involving two bits and detect and correct errors involving a single bit.